vpp: sr: correct the sr core0 enable switch operation [1/1]

vpp: sr: correct the sr core0 enable switch operation [1/1]

PD#SWPL-5113

Problem:
SR core0 enable switch register is latched as default. It
will cause the screen flicker when operating this bit in vsync.
Because the frame size will be out of sync with back-end module.

Solution:
1. For g12a, no latch ctrl. So did not disable sr core2 enable bit.
2. For g12b/tl1, disable the latch function.

Verify:
Verified on U212/w400/x301

Change-Id: I54027b71ef8a6066004b3bd32ed1633b4bfa351c
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>