PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r)
authorGrant Erickson <gerickson@nuovations.com>
Wed, 9 Jul 2008 18:55:46 +0000 (11:55 -0700)
committerStefan Roese <sr@denx.de>
Fri, 11 Jul 2008 11:18:12 +0000 (13:18 +0200)
commit5b457d00730d4aa0c6450d21a9104723e606fb98
tree3f89dc42f698f5f891a3fba0d712fc705b61c2c3
parent0ce5c8675bb2c61f1d71fb97f0bbe822663fb93d
PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r)

While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM
controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in
the 405EX(r), SDRAM_MCSTAT has a different DCR value.

Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF
which causes SDRAM initialization to periodically fail since it can
prematurely indicate SDRAM ready status.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
include/asm-ppc/ppc4xx-sdram.h