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(parent: 9a736cf) | patch
AArch64: disallow "fmov sD, #-0.0" during assembly.
authorTim Northover <tnorthover@apple.com>
Tue, 7 Apr 2015 22:49:47 +0000 (22:49 +0000)
committerTim Northover <tnorthover@apple.com>
Tue, 7 Apr 2015 22:49:47 +0000 (22:49 +0000)
commit5b44f1ba199d78bb3e5319fc7958d0a2ba90c168
tree4ad99832bc542efeeb00cb0b23ab12077ca5765ctree | snapshot
parent9a736cf29fc13c6330e0c7d43dec15168fe14b1fcommit | diff
AArch64: disallow "fmov sD, #-0.0" during assembly.

We weren't checking the sign of the floating point immediate before translating
it to "fmov sD, wzr". Similarly for D-regs.

Technically "movi vD.2s, #0x80, lsl #24" would work most of the time, but it's
not a blessed alias (and I don't think it should be since people expect writing
sD to zero out the high lanes, and there's no dD equivalent). So an error it is.

rdar://20455398

llvm-svn: 234372
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp diff | blob | history
llvm/test/MC/AArch64/arm64-fp-encoding-error.s [new file with mode: 0644] blob
Domain: System / Toolchain;