GlobalISel: Change representation of shuffle masks
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 13 Aug 2019 15:34:38 +0000 (15:34 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 13 Aug 2019 15:34:38 +0000 (15:34 +0000)
commit5af9cf042f21d6b044f8925b581a8f089d739bc5
tree1c7016ee055287ef20d67cdbf8a5ff6d9634dfb8
parent8a033a9e3fb96b9a1099325c4cd218c1c979d9d9
GlobalISel: Change representation of shuffle masks

Currently shufflemasks get emitted as any other constant, and you end
up with a bunch of virtual registers of G_CONSTANT with a
G_BUILD_VECTOR. The AArch64 selector then asserts on anything that
doesn't fit this pattern. This isn't an ideal representation, and
should avoid legalization and have fewer opportunities for a
representational error.

Rather than invent a new shuffle mask operand type, similar to what
ShuffleVectorSDNode does, just track the original IR Constant mask
operand. I don't completely like the idea of adding another link to
the IR, but MIR is already quite dependent on IR constants already,
and this will allow sharing the shuffle mask utility functions with
the IR.

llvm-svn: 368704
25 files changed:
llvm/include/llvm/CodeGen/MachineInstrBuilder.h
llvm/include/llvm/CodeGen/MachineOperand.h
llvm/include/llvm/Target/GenericOpcodes.td
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/lib/CodeGen/MIRParser/MILexer.cpp
llvm/lib/CodeGen/MIRParser/MILexer.h
llvm/lib/CodeGen/MIRParser/MIParser.cpp
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/lib/CodeGen/MachineOperand.cpp
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid0.mir [new file with mode: 0644]
llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid1.mir [new file with mode: 0644]
llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid2.mir [new file with mode: 0644]
llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid3.mir [new file with mode: 0644]
llvm/test/CodeGen/MIR/AArch64/parse-shufflemask.mir [new file with mode: 0644]
llvm/test/MachineVerifier/test_g_shuffle_vector.mir [new file with mode: 0644]