Hardware instruction set support for crossgen2 (#33274)

Hardware instruction set support for crossgen2 (#33274)

- Add support for the --instruction-set parameter as described in #226 .
NOTE: As the abi for Vector parameters is not yet stable, support for the --instruction-set parameter is only enabled if --inputbubble is also enabled. Parallel work to stabilize the abi is in progress, but is not complete.
ALSO NOTE: The names of the instruction sets are shared with mono, and don't follow the names in issue #226
- Add concept of baseline instruction set support to R2R file format
- Can be applied at a per method level or at the entire R2R file level
  - R2RDump support for dumping the extra data
- Refactor how support for hardware intrinsics beyond SSE2 support are handled in crossgen2
- Add feature to the JIT to detect which hardware features are actually used
  - Tell the JIT unconditionally that SSE42+Lzcnt+Popcnt+Pclmulqdq are supported
  - But if support beyond the --instruction-set specified baseline is used, notate the method with a per-method instruction set support fixup.
  - This enables usage of many intrinsics in corelib with greater efficiency than today
  - This enables usage of SSE42 and below intrinsics safely in non-CoreLib code. Use of higher level intrinsics in non CoreLib code will generate code which does not use the higher level intrinsic, and note that the method's code should not be used in the presence of hardware which does support greater CPU capabilities.
  - In the future a logical enhancement of this work would be to generate multiple bodies of code to handle these more complex cases.
  - In combination with the --instruction-set argument, if Avx2 is enabled, then the logic gracefully adds a dependency on Avx2 capability and Vector<T> becomes useable by crossgen'd code.