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mtd: nand: sunxi: adapt clk_rate to tWB, tADL, tWHR and tRHW timings
authorBoris Brezillon <boris.brezillon@free-electrons.com>
Wed, 11 Nov 2015 21:30:30 +0000 (22:30 +0100)
committerBoris Brezillon <boris.brezillon@free-electrons.com>
Tue, 19 Apr 2016 20:05:38 +0000 (22:05 +0200)
commit5abcd95d8c69008c72d54d7763e0ee2b5df84ac4
tree5eb62927cb19084d9b14071a54c2b24e55736634tree | snapshot
parent2d43457f79e48ee427666fdbfe9a53f35d3a1672commit | diff
mtd: nand: sunxi: adapt clk_rate to tWB, tADL, tWHR and tRHW timings

Adapt the NAND controller clk rate to the tWB, tADL, tWHR and tRHW
timings instead of returning an error when the maximum clk divisor is
not big enough to provide an appropriate timing.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
drivers/mtd/nand/sunxi_nand.c diff | blob | history
Domain: System / Kernel;