drm/amd/display: Add support for toggling DFS bypass
authorNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tue, 21 Aug 2018 19:36:49 +0000 (14:36 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 27 Aug 2018 16:09:50 +0000 (11:09 -0500)
commit5a83c93249098df2ee3b0039ec8f4495b959fcd0
tree0d12ba48b1c98165fe1f0265c2fc2b1e9a7e8780
parent1c8faa9aa0cc1ccf02bed608d23966b7347d71a6
drm/amd/display: Add support for toggling DFS bypass

[Why]

If the hardware supports DFS bypass it will always be enabled after
creation of the DCCG. DFS bypass should only be enabled when
the current stream consists of a single embedded panel and the
minimum display clock is below the DFS bypass threshold.

[How]

Add a function to the DCCG table that updates the DFS bypass state
when setting the bandwidth. If the DFS bypass state is changed, the
clock needs to be reprogrammed to reflect this before the DPREFCLK
is updated for audio endpoints. The existing display clock value
is used as the target display clock value when reprogramming since the
resulting change will be equal or larger to the current value.

These changes only specifically target dce110 but do offer a framework
for support on other applicable targets.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h