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[RISCV] Add test cases for SRO/SLO with shift amounts masked to bitwidth-1. NFC
authorCraig Topper <craig.topper@sifive.com>
Sat, 23 Jan 2021 23:45:51 +0000 (15:45 -0800)
committerCraig Topper <craig.topper@sifive.com>
Sat, 23 Jan 2021 23:45:51 +0000 (15:45 -0800)
commit5a73daf907873a8757213932f814361a59f02da5
tree0b223742aa75765cbbd004dab074356a54fbf2cctree | snapshot
parentd2927f786e877410d90c1e6f0e0c7d99524529c5commit | diff
[RISCV] Add test cases for SRO/SLO with shift amounts masked to bitwidth-1. NFC

The sro/slo instructions ignore extra bits in the shift amount,
so we can ignore the mask just like we do for sll, srl, and sra.
llvm/test/CodeGen/RISCV/rv32Zbp.ll diff | blob | history
llvm/test/CodeGen/RISCV/rv64Zbp.ll diff | blob | history
Domain: System / Toolchain;