[RISCV] Remove earlyclobber from compares with LMUL<=1.
authorCraig Topper <craig.topper@sifive.com>
Tue, 1 Jun 2021 15:50:18 +0000 (08:50 -0700)
committerCraig Topper <craig.topper@sifive.com>
Tue, 1 Jun 2021 16:08:11 +0000 (09:08 -0700)
commit5a5219a0f961b91253dc3fdb4b33e088b199b451
tree6cc760d427e84a80c9826c00b11ffb90ffa70f15
parentecfca427f9601a7789c0703582cff92e7a3277c0
[RISCV] Remove earlyclobber from compares with LMUL<=1.

Compares are considered a narrowing operation for register overlap.
I believe for LMUL<=1 they meet this exception to allow overlap

"The destination EEW is smaller than the source EEW and the overlap is in the
lowest-numbered part of the source register group"

Both the result and the sources will occupy a single register for
LMUL<=1 so the overlap would always be in the "lowest-numbered part".

Reviewed By: frasercrmck, HsiangKai

Differential Revision: https://reviews.llvm.org/D103336
12 files changed:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
llvm/test/CodeGen/RISCV/rvv/select-int.ll
llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll