Recommit "[RISCV] Enable subregister liveness tracking for RVV."
authorCraig Topper <craig.topper@sifive.com>
Tue, 21 Jun 2022 03:20:00 +0000 (20:20 -0700)
committerCraig Topper <craig.topper@sifive.com>
Tue, 21 Jun 2022 03:46:06 +0000 (20:46 -0700)
commit59cde2133d8f2488171404c3e1a8fc302f0249c3
tree38c17696843704f704d2ed4b871370fb2bae7824
parent163c77b2e0831853b59cdd24ece9637f8a19cc79
Recommit "[RISCV] Enable subregister liveness tracking for RVV."

The failure that caused the previous revert has been fixed
by https://reviews.llvm.org/D126048

Original commit message:

RVV makes heavy use of subregisters due to LMUL>1 and segment
load/store tuples. Enabling subregister liveness tracking improves the quality
of the register allocation.

I've added a command line that can be used to turn it off if it causes compile
time or functional issues. I used the command line to keep the old behavior
for one interesting test case that was testing register allocation.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D128016
38 files changed:
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-load.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll