clk: sunxi: Add NAND clocks and resets
authorSamuel Holland <samuel@sholland.org>
Sun, 22 Jan 2023 22:06:31 +0000 (16:06 -0600)
committerAndre Przywara <andre.przywara@arm.com>
Fri, 28 Apr 2023 00:06:57 +0000 (01:06 +0100)
commit59c1ddd2c51b2ff13801a9cde8121242bfcd8629
tree05ec3c08f0dd5f0a622b85b03e453f090f7921b2
parent9a4aa31ad514a534e57b2607df327cb4f93b87bc
clk: sunxi: Add NAND clocks and resets

Currently NAND clock setup is done in board code, both in SPL and in
U-Boot proper. Add the NAND clocks/resets here so they can be used by
the "full" NAND driver once it is converted to the driver model.

The bit locations are copied from the Linux CCU drivers.

Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
drivers/clk/sunxi/clk_a10.c
drivers/clk/sunxi/clk_a10s.c
drivers/clk/sunxi/clk_a23.c
drivers/clk/sunxi/clk_a31.c
drivers/clk/sunxi/clk_a64.c
drivers/clk/sunxi/clk_a80.c
drivers/clk/sunxi/clk_a83t.c
drivers/clk/sunxi/clk_h3.c
drivers/clk/sunxi/clk_h6.c
drivers/clk/sunxi/clk_h616.c
drivers/clk/sunxi/clk_r40.c