projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 2060a16) | patch
[X86] Fix register resizings for inline assembly register operands.
authorNirav Dave <niravd@google.com>
Thu, 13 Sep 2018 20:33:56 +0000 (20:33 +0000)
committerNirav Dave <niravd@google.com>
Thu, 13 Sep 2018 20:33:56 +0000 (20:33 +0000)
commit59ad1c845787238560142d7608bc9433cbe9eaa0
tree6f90ddda31baffc7c60e772b5725c8320c6dfb91tree | snapshot
parent2060a16dfd6b83a12d7388de56b8ba56886950a7commit | diff
[X86] Fix register resizings for inline assembly register operands.

When replacing a named register input to the appropriately sized
sub/super-register. In the case of a 64-bit value being assigned to a
register in 32-bit mode, match GCC's assignment.

Reviewers: eli.friedman, craig.topper

Subscribers: nickdesaulniers, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D51502

llvm-svn: 342175
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/lib/Target/X86/X86RegisterInfo.td diff | blob | history
llvm/test/CodeGen/X86/atomic_mi.ll diff | blob | history
llvm/test/CodeGen/X86/avx512-regcall-Mask.ll diff | blob | history
llvm/test/CodeGen/X86/physreg-pairs-error.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/physreg-pairs.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll diff | blob | history
Domain: System / Toolchain;