i2c: piix4: Enable EFCH MMIO for Family 17h+
authorTerry Bowman <terry.bowman@amd.com>
Wed, 9 Feb 2022 17:27:17 +0000 (11:27 -0600)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 25 May 2022 07:57:23 +0000 (09:57 +0200)
commit5996d3601e774f7875537e5ba7aea0abf77441b0
tree97e2c6c09ba595f34ecbf2928803cfd7464b3633
parentd46b4ff3bb0bf707253ccba412ebf9a6b3aa1433
i2c: piix4: Enable EFCH MMIO for Family 17h+

commit 6cf72f41808ab5db1d7718b999b3ff0166e67e45 upstream.

Enable EFCH MMIO using check for SMBus PCI revision ID value 0x51 or
greater. This PCI revision ID check will enable family 17h and future
AMD processors with the same EFCH SMBus controller HW.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Cc: Mario Limonciello <Mario.Limonciello@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/i2c/busses/i2c-piix4.c