x86: Optimizing memcpy for AMD Zen architecture.
authorSajan Karumanchi <sajan.karumanchi@amd.com>
Wed, 28 Oct 2020 07:35:33 +0000 (13:05 +0530)
committerFlorian Weimer <fweimer@redhat.com>
Wed, 28 Oct 2020 08:57:14 +0000 (09:57 +0100)
commit59803e81f96b479c17f583b31eac44b57591a1bf
treea580e2fd555e4d83fb095b2f2523cb180e5df4c1
parent641a12484562b3a740b940620ac2c47a626c9861
x86: Optimizing memcpy for AMD Zen architecture.

Modifying the shareable cache '__x86_shared_cache_size', which is a
factor in computing the non-temporal threshold parameter
'__x86_shared_non_temporal_threshold' to optimize memcpy for AMD Zen
architectures.
In the existing implementation, the shareable cache is computed as 'L3
per thread, L2 per core'. Recomputing this shareable cache as 'L3 per
CCX(Core-Complex)' has brought in performance gains.
As per the large bench variant results, this patch also addresses the
regression problem on AMD Zen architectures.

Reviewed-by: Premachandra Mallappa <premachandra.mallappa@amd.com>
sysdeps/x86/cacheinfo.h