[AMDGPU] More selectively attach implicit operands to agpr spills
authorJeffrey Byrnes <Jeffrey.Byrnes@amd.com>
Fri, 6 Jan 2023 00:38:25 +0000 (16:38 -0800)
committerJeffrey Byrnes <Jeffrey.Byrnes@amd.com>
Mon, 9 Jan 2023 23:10:06 +0000 (15:10 -0800)
commit596c5581556cbd4103d982066fb76e745fb8480e
tree56731427e9b24ef0f7cb84d2f3529146bce45011
parent275ff33abf22689b8eef15a2d03d0025ba35a9c2
[AMDGPU] More selectively attach implicit operands to agpr spills

Implicit def operands are needed when we spill partially undef super registers by each individual subregister. The implicit-def operands will allow us to lower spills without the verifier complaining. Currently, we are overzeously attaching implicit operands, when we really only need them on the first sub reg spill op. By more selectively attached the implicit ops, we will free up some unneeded dependencies for the post-ra scheduler.

Moreover, this enables a previously incorrect optimization / resolves a correctness issue in indirectCopyToAGPR. When lowering AGPR copies on GFX908, we can improve CodeGen by reusing accvgpr_writes. However, we could not reliably determine which agprs accvgpr_writes actually define due to implicit-defs.

Differential Revision: https://reviews.llvm.org/D141101
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
llvm/test/CodeGen/AMDGPU/spill-agpr.mir
llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir