AMDGPU: Regenerate some mir test checks with -NEXT
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Sat, 18 Dec 2021 15:07:00 +0000 (10:07 -0500)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Sat, 18 Dec 2021 15:46:15 +0000 (10:46 -0500)
commit591371f7df3cee0429c85f2aeb4a848df8888386
treed9bc4fb8bc42744fdedf761e713618ba2760a07a
parent3362fa59ec406ba1eebe9e9ee59a04b675ef2439
AMDGPU: Regenerate some mir test checks with -NEXT
64 files changed:
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-build-vector.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir