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(parent: e11f804) | patch
clk: renesas: r9a07g043: Add SDHI clock and reset entries
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 2 Apr 2022 07:46:26 +0000 (08:46 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 13 Apr 2022 10:30:19 +0000 (12:30 +0200)
commit59086e4193f4fc920a23d2045a473f62450b4269
tree89ccc4fd387dfa32c507ed096f795b7894e6762etree | snapshot
parente11f804afc12e1c622f0a6f966fafd05b7022f8acommit | diff
clk: renesas: r9a07g043: Add SDHI clock and reset entries

Add SDHI{0,1} mux, clock and reset entries to CPG driver

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g043-cpg.c diff | blob | history
Domain: System / Kernel;