FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.
authorKumar Gala <galak@kernel.crashing.org>
Tue, 26 Aug 2008 20:01:29 +0000 (15:01 -0500)
committerWolfgang Denk <wd@denx.de>
Wed, 27 Aug 2008 00:05:58 +0000 (02:05 +0200)
commit58e5e9aff147e8c7e2bc1406bf9384f65f020ffa
treea246c5ded0e1cdc32687c52b15483b11a0966795
parentf784e32b4bce0013983506b11af4b85b8ca3d36e
FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.

The main purpose of this rewrite it to be able to share the same
initialization code on all FSL PowerPC products that have DDR
controllers.  (83xx, 85xx, 86xx).

The code is broken up into the following steps:
GET_SPD
COMPUTE_DIMM_PARMS
COMPUTE_COMMON_PARMS
GATHER_OPTS
ASSIGN_ADDRESSES
COMPUTE_REGS
PROGRAM_REGS

This allows us to share more code an easily allow for board specific code
overrides.

Additionally this code base adds support for >4G of DDR and provides a
foundation for supporting interleaving on processors with more than one
controller.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 files changed:
Makefile
cpu/mpc85xx/Makefile
cpu/mpc86xx/Makefile
cpu/mpc8xxx/ddr/Makefile [new file with mode: 0644]
cpu/mpc8xxx/ddr/common_timing_params.h [new file with mode: 0644]
cpu/mpc8xxx/ddr/ctrl_regs.c [new file with mode: 0644]
cpu/mpc8xxx/ddr/ddr.h [new file with mode: 0644]
cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h [new file with mode: 0644]
cpu/mpc8xxx/ddr/lc_common_dimm_params.c [new file with mode: 0644]
cpu/mpc8xxx/ddr/main.c [new file with mode: 0644]
cpu/mpc8xxx/ddr/options.c [new file with mode: 0644]
cpu/mpc8xxx/ddr/util.c [new file with mode: 0644]
include/asm-ppc/fsl_ddr_sdram.h [new file with mode: 0644]