drm/i915/hdcp: update cp_irq_count_cached in intel_dp_hdcp2_read_msg()
authorJuston Li <juston.li@intel.com>
Thu, 19 Aug 2021 18:48:33 +0000 (11:48 -0700)
committerAnshuman Gupta <anshuman.gupta@intel.com>
Thu, 9 Sep 2021 07:38:22 +0000 (13:08 +0530)
commit58cfa3297aa0779e18b7cbb5e6c6301f97c5f776
treecf3ef9c0ac596ff5cbe907f90f33477c29a45d4f
parentddb8cd4eee01049f34194affaf7d027bfa400e2c
drm/i915/hdcp: update cp_irq_count_cached in intel_dp_hdcp2_read_msg()

Update cp_irq_count_cached when reading messages rather than when
writing a message to make sure the value is up to date and not
stale from a previously handled CP_IRQ.

AKE flow  doesn't always respond to a read with a ACK write msg.
E.g. AKE_Send_Pairing_Info will "timeout" because we received
a CP_IRQ for reading AKE_Send_H_Prime but no write occurred between that
and reading AKE_Send_Pairing_Info so cp_irq_count_cached is stale
causing the wait to return right away rather than waiting for a new
CP_IRQ.

Signed-off-by: Juston Li <juston.li@intel.com>
Acked-by: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Tested-by: Suraj K <suraj.kandpal@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210819184835.1181323-2-juston.li@intel.com
drivers/gpu/drm/i915/display/intel_dp_hdcp.c