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author	Craig Topper <craig.topper@sifive.com>
	Tue, 6 Jun 2023 18:59:12 +0000 (11:59 -0700)
committer	Craig Topper <craig.topper@sifive.com>
	Tue, 6 Jun 2023 18:59:12 +0000 (11:59 -0700)
commit	58b2d652af49ee9d9ff2af6edd7f67f23b26bfee
tree	559f5a34b40eeaef79818e523b05162871002b96	tree \| snapshot
parent	e468f07550c56eeb49659d02c7c5c3f79f53db6f	commit \| diff

[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).

Where C is a simm32.

This costs an extra temporary register, but avoids a constant pool.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D152236

30 files changed:

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVISelLowering.cpp		diff \| blob \| history
llvm/test/CodeGen/RISCV/bswap-bitreverse.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/div-by-constant.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/div.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/pr56457.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64xtheadbb.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64zbb.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/sextw-removal.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/split-urem-by-constant.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll		diff \| blob \| history

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