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(parent: 317e00b) | patch
phy: qcom: edp: Perform lane configuration
authorBjorn Andersson <bjorn.andersson@linaro.org>
Wed, 10 Aug 2022 04:07:43 +0000 (21:07 -0700)
committerVinod Koul <vkoul@kernel.org>
Tue, 30 Aug 2022 05:31:23 +0000 (11:01 +0530)
commit5894ff12c7ec0bd5960c6f1d91b64674d9ffb9bf
treeb0dacb799c7720e648a49a66ee7166664bf99df1tree | snapshot
parent317e00bbf950b5dd83f18f6771c3e402485052eacommit | diff
phy: qcom: edp: Perform lane configuration

The TRANSCIEVER_BIAS_EN, HIGHZ_DRVR_EN and PHY_CFG_1 registers are used
for lane configuration, with the currently hard coded configuration
being a mix of 2 and 4 lane (effectively 2-lane).

Properly implement lane configuration for 1, 2 and 4 lanes.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220810040745.3582985-4-bjorn.andersson@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/qualcomm/phy-qcom-edp.c diff | blob | history
Domain: System / Kernel;