net/macb: fix ISR clear-on-write behavior only for some SoC
authorNicolas Ferre <nicolas.ferre@atmel.com>
Tue, 14 May 2013 03:00:16 +0000 (03:00 +0000)
committerDavid S. Miller <davem@davemloft.net>
Tue, 14 May 2013 20:04:02 +0000 (13:04 -0700)
commit581df9e1944194bfcabc57e1efae79b0fe171d6f
treec9965f5d51aaadee4bbaf3b1608876ac743015b3
parentfaff57a92ba1d7247c5e86ecea2886d2c9d54507
net/macb: fix ISR clear-on-write behavior only for some SoC

Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using the Design Configuration Register 1 information and a capability
property to actually activate this clear-on-write behavior on ISR.

Reported-by: Hein Tibosch <hein_tibosch@yahoo.es>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Hein Tibosch <hein_tibosch@yahoo.es>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/cadence/macb.c
drivers/net/ethernet/cadence/macb.h