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(parent: 6f14c73) | patch
When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8...
authorEvan Cheng <evan.cheng@apple.com>
Thu, 30 Jul 2009 23:29:25 +0000 (23:29 +0000)
committerEvan Cheng <evan.cheng@apple.com>
Thu, 30 Jul 2009 23:29:25 +0000 (23:29 +0000)
commit5811ab5cf344bc6715bf259b348576f50d4e1c34
tree046131b877734fa7f846211222fa1939cb09a39atree | snapshot
parent6f14c73087ba24f0f48ba07afb3cc6466d468acccommit | diff
When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.

llvm-svn: 77642
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp diff | blob | history
llvm/lib/Target/ARM/ARMBaseRegisterInfo.h diff | blob | history
llvm/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll [new file with mode: 0644] blob
Domain: System / Toolchain;