clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
authorShawn Guo <shawn.guo@linaro.org>
Tue, 21 Mar 2017 08:38:21 +0000 (16:38 +0800)
committerMichael Turquette <mturquette@baylibre.com>
Wed, 12 Apr 2017 16:51:29 +0000 (18:51 +0200)
commit5790d801762c588c63b41fbdbdb8295cfd6036e6
treea10c8e3f63c2d2b96f83cace96496b095ac1cae1
parentcf091ee994ec266e33c3a305d6fc8c5ccb1f8acd
clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks

To support VOU VGA display driver with different modes, we need to set
flag for a few clocks, so that clk_set_rate() call in VOU driver can get
VGA device desired pixel rate.

While at it, the divider between pll_vga and clk_vga gets corrected, as
it's 1:1 instead of 1:2.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
drivers/clk/zte/clk-zx296718.c