projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: bcea3a7) | patch
[AMDGPU] Make GCNRegBankReassign assign based on subreg banks
authorCarl Ritson <carl.ritson@amd.com>
Tue, 4 Aug 2020 03:20:12 +0000 (12:20 +0900)
committerCarl Ritson <carl.ritson@amd.com>
Tue, 4 Aug 2020 03:54:44 +0000 (12:54 +0900)
commit57899934eab18bbcab3482cc3ef862b0a1617ad0
tree984e02c6653935c61710b53e4202d5624ac9731btree | snapshot
parentbcea3a7a288e0b5ac977f90c46e4eef7946467e7commit | diff
[AMDGPU] Make GCNRegBankReassign assign based on subreg banks

When scavenging consider the sub-register of the source operand
to determine the bank of a candidate register (not just sub0).
Without this it is possible to introduce an infinite loop,
e.g. $sgpr15_sgpr16_sgpr17 can be assigned for a conflict between
$sgpr0 and SGPR_96:sub1.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D84910
llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/regbank-reassign-wave64.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/regbank-reassign.mir diff | blob | history
Domain: System / Toolchain;