phy: stm32: ensure pll is disabled before phys creation
authorAmelie Delaunay <amelie.delaunay@foss.st.com>
Tue, 5 Jan 2021 09:05:23 +0000 (10:05 +0100)
committerVinod Koul <vkoul@kernel.org>
Wed, 13 Jan 2021 15:10:21 +0000 (20:40 +0530)
commit56bf858edd17bd4a320aca1a10aea7dbfb0c6699
tree7b862cb0233d2ec1af53f097e65434d19ae4d19e
parent04edf6d6e22b76aacb23d545a9fe642573f73c9b
phy: stm32: ensure pll is disabled before phys creation

To ensure a good balancing of regulators, force PLL disable either by
reset or by clearing the PLLEN bit.
If waiting the powerdown pulse delay isn't enough, return -EPROBE_DEFER
instead of polling the PLLEN bit, which will be low at the next probe.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20210105090525.23164-5-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/st/phy-stm32-usbphyc.c