[AMDGPU] Callee must always spill writelane VGPRs
authorChristudasan Devadasan <Christudasan.Devadasan@amd.com>
Mon, 13 Jun 2022 13:12:02 +0000 (18:42 +0530)
committerChristudasan Devadasan <Christudasan.Devadasan@amd.com>
Sat, 17 Dec 2022 05:41:42 +0000 (11:11 +0530)
commit5692a7e84e1273921099f9fbbaf353cd000df9bb
tree3acef8bd9405e56da564a732a148b5e447aa578e
parentcc037e17907dadc5ecb06bce61ce48a6627b274d
[AMDGPU] Callee must always spill writelane VGPRs

Since the writelane instruction used for SGPR spills can
modify inactive lanes, the callee must preserve the VGPR
this instruction modifies even if it was marked Caller-saved.

Reviewed By: arsenm, nhaehnle

Differential Revision: https://reviews.llvm.org/D124192
17 files changed:
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
llvm/test/CodeGen/AMDGPU/frame-index.mir
llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll