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(parent: 5e34055) | patch
crypto: hisilicon/sec - fix the CTR mode BD configuration
authorKai Ye <yekai13@huawei.com>
Sat, 22 Jan 2022 08:13:11 +0000 (16:13 +0800)
committerHerbert Xu <herbert@gondor.apana.org.au>
Mon, 31 Jan 2022 00:21:45 +0000 (11:21 +1100)
commit566f060f5453e906dd4195c7e94f1fd25d2c99bb
tree30cbe42e8625e8b1b0058d5984efc44c89f7596atree | snapshot
parent5e340558c5c7f64504ef1f4d31af152f26705261commit | diff
crypto: hisilicon/sec - fix the CTR mode BD configuration

The CTR counter is 32bit rollover default on the BD.
But the NIST standard is 128bit rollover. it cause the
testing failed, so need to fix the BD configuration.

Signed-off-by: Kai Ye <yekai13@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
drivers/crypto/hisilicon/sec2/sec_crypto.c diff | blob | history
drivers/crypto/hisilicon/sec2/sec_crypto.h diff | blob | history
Domain: System / Kernel;