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RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}
authorPalmer Dabbelt <palmer@sifive.com>
Tue, 2 Oct 2018 19:14:55 +0000 (12:14 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 23 Oct 2018 00:03:35 +0000 (17:03 -0700)
commit566d6c428eadf9dc06df8b2195dff58d9a97c9e6
tree026f0ab6a209ce19657e83d9dd7114cf9e438b30tree | snapshot
parent1ed4237ab616a05225e11d07bf42d5474deec905commit | diff
RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}

These are just hard coded in the RISC-V port, which doesn't make any
sense.  We should probably be setting these from device tree entries
when they exist, but for now I think it's saner to just leave them all
as their default values.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
arch/riscv/kernel/cacheinfo.c diff | blob | history
Domain: System / Kernel;