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[InstCombine] Handle (X & C2) < C1 --> (X & C2) == 0
authorCraig Topper <craig.topper@intel.com>
Wed, 20 Sep 2017 21:18:17 +0000 (21:18 +0000)
committerCraig Topper <craig.topper@intel.com>
Wed, 20 Sep 2017 21:18:17 +0000 (21:18 +0000)
commit562bf99ee61dbc28901253590780981c45e38e72
treea31aa230492206272ba474b5e350a46baad110f5tree | snapshot
parent9b593a69385034e11afb41e87b4d4752e88aff37commit | diff
[InstCombine] Handle (X & C2) < C1 --> (X & C2) == 0

We already did (X & C2) > C1 --> (X & C2) != 0, if any bit set in (X & C2) will produce a result greater than C1. But there is an equivalent inverse condition with <= C1 (which will be canonicalized to < C1+1)

Differential Revision: https://reviews.llvm.org/D38065

llvm-svn: 313819
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp diff | blob | history
llvm/test/Transforms/InstCombine/icmp.ll diff | blob | history
Domain: System / Toolchain;