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[X86-64] Fix 256-bit SET0 lowering for non-VLX targets
authorDavid Greene <greened@obbligato.org>
Tue, 28 May 2019 15:37:01 +0000 (15:37 +0000)
committerDavid Greene <greened@obbligato.org>
Tue, 28 May 2019 15:37:01 +0000 (15:37 +0000)
commit561fcc0d63caca46e46a746db482a1c6895b2ac4
tree03e64e5f43c058f13f56c24e964e43d39e29984etree | snapshot
parentebe22a1774ed433534a63af0bf5fdc5b5bd821b4commit | diff
[X86-64] Fix 256-bit SET0 lowering for non-VLX targets

If we don't have VLX then 256-bit SET0 should be lowered
to VPXOR with ZMM registers.  This restores functionality
accidentally removed by r309926.

Differential Revision: https://reviews.llvm.org/D62415

llvm-svn: 361843
llvm/lib/Target/X86/X86InstrInfo.cpp diff | blob | history
llvm/test/CodeGen/X86/avx512f-256-set0.mir [new file with mode: 0644] blob
Domain: System / Toolchain;