Fix lcl fld addr. (#39424)
authorSergey Andreenko <seandree@microsoft.com>
Fri, 24 Jul 2020 21:45:48 +0000 (14:45 -0700)
committerGitHub <noreply@github.com>
Fri, 24 Jul 2020 21:45:48 +0000 (14:45 -0700)
commit557c7aff0d63fbb1bf687be215ec1726625abc2a
tree085422c2ccc784608968fce6bc720728c6c0d8fc
parent43d558387cc0d48e45f9c1ca960f912c425c1fa1
Fix lcl fld addr. (#39424)

* Add a repro test.

* Small ref.

Combine long chains of `addr->OperGet() == GT_* ||` with `GT_LCL_VAR_ADDR` using `OperIs` to simplify future changes.

* Add an assert that would fire in the repro test.

`emitter::emitHandleMemOp` has special logic for contained `memBase` and but the last block does not
expect a contained node. A contained node doesn't produce a register so it is not correct to use result
of `GetRegNum()` from a contained node as a valid register.
However, adding an assert to `GetRegNum()` that `!this->isContained` is a bigger task that is out of this PR.

* Assert that `LCL_FLD_ADDR` is not contained in `genPutArgStk(Split)`

We have contained `LCL_VAR_ADDR` support there but make sure that contained `LCL_FLD_ADDR` can't reach it.

* Contain `GT_LCL_FLD_ADDR` under HW_INTRINSIC.

This is an additional optimization that makes future changes simpler.

* Add contained checks.

In all these places we expect `LCL_VAR_ADDR` to be contained.
If we had gotten a `LCL_VAR_ADDR` that is not contained we would have instantiated `LCL_VAR_ADDR` twice:
in the register and the parent instruction.
The register value would have been unused.

* Support `FLD_ADDR` where `LCL_ADDR` is supported.

However, fire an assert if we think that this path is unreachable for now.

* Delete asserts in the  reachable blocks.

We have coverage for this asserts in the following tests:
hwintrinsic 478: Ssse3_ro
instr 11645: Runtime_39403
instr 1028 : Aes_ro
hwintrinsic 716: pmi of Microsoft.Diagnostics.Tracing.TraceEvent

* Review response.

* Add repro cases.

Delete the rest `assert(!"don't expect GT_LCL_FLD_ADDR");`.

* Use `GetLclOffs` from `LclVarCommon`.

* missed file.
src/coreclr/src/jit/codegenarmarch.cpp
src/coreclr/src/jit/codegenxarch.cpp
src/coreclr/src/jit/emitxarch.cpp
src/coreclr/src/jit/hwintrinsiccodegenxarch.cpp
src/coreclr/src/jit/instr.cpp
src/coreclr/src/jit/lowerxarch.cpp
src/tests/JIT/Regression/JitBlue/Runtime_39403/Runtime_39403.cs [new file with mode: 0644]
src/tests/JIT/Regression/JitBlue/Runtime_39403/Runtime_39403.csproj [new file with mode: 0644]
src/tests/JIT/Regression/JitBlue/Runtime_39424/Runtime_39424.il [new file with mode: 0644]
src/tests/JIT/Regression/JitBlue/Runtime_39424/Runtime_39424.ilproj [new file with mode: 0644]