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(parent: 95d9440) | patch
Optimize vector select from all 0s or all 1s
authorMichael Liao <michael.liao@intel.com>
Thu, 11 Apr 2013 05:15:54 +0000 (05:15 +0000)
committerMichael Liao <michael.liao@intel.com>
Thu, 11 Apr 2013 05:15:54 +0000 (05:15 +0000)
commit55658d42228e8dbfa8d74d1b37e330aaee284c00
tree248bdaeb5819f711d4e863163bd0ca50a34003b2tree | snapshot
parent95d9440348a8437fb792052a2238d972bf884bdacommit | diff
Optimize vector select from all 0s or all 1s

As packed comparisons in AVX/SSE produce all 0s or all 1s in each SIMD lane,
vector select could be simplified to AND/OR or removed if one or both values
being selected is all 0s or all 1s.

llvm-svn: 179267
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/select-with-and-or.ll [new file with mode: 0644] blob
Domain: System / Toolchain;