review.tizen.org Git - platform/upstream/llvm.git/commit

projects / platform / upstream / llvm.git / commit

author	Matt Arsenault <Matthew.Arsenault@amd.com>
	Sun, 12 Jan 2020 22:10:18 +0000 (17:10 -0500)
committer	Matt Arsenault <arsenm2@gmail.com>
	Mon, 13 Jan 2020 03:44:51 +0000 (22:44 -0500)
commit	555e7ee04cb5c44e0b11a2eda999e6910b4b27e1
tree	72f1d2809df3e21b8d40e89b2a612e7b6828a78b	tree \| snapshot
parent	a10527cd3731e2ef246c4797fb099385a948f62f	commit \| diff

AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs

We don't use the xexec register classes for arbitrary values
anymore. Avoids a test variance beween GlobalISel and SelectionDAG>

39 files changed:

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir		diff \| blob \| history

Domain: System / Toolchain;

RSS Atom