clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.
authorEric Anholt <eric@anholt.net>
Tue, 17 Jan 2017 20:31:55 +0000 (07:31 +1100)
committerStephen Boyd <sboyd@codeaurora.org>
Sat, 21 Jan 2017 00:22:54 +0000 (16:22 -0800)
commit55486091bd1e1c5ed28c43c0d6b3392468a9adb5
treee4faf5b7fd4ed0f561cec23cdba2dee39610b7dc
parent0c744ea4f77d72b3dcebb7a8f2684633ec79be88
clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.

Our core PLLs are intended to be configured once and left alone.  With
the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would
change PLLD just to get closer to the requested DSI clock, thus
changing PLLD_PER, the UART and ethernet PHY clock rates downstream of
it, and breaking ethernet.

We *do* want PLLH to change so that PLLH_AUX can be exactly the value
we want, though.  Thus, we need to have a per-divider policy of
whether to pass rate changes up.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/bcm/clk-bcm2835.c