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drm/amdgpu: Add MES KIQ clear to tell RLC that KIQ is dequeued
authorYifan Zha <Yifan.Zha@amd.com>
Wed, 29 Mar 2023 09:18:47 +0000 (17:18 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 11 Apr 2023 22:03:35 +0000 (18:03 -0400)
commit554836cc24411e4d3645db5392655f8d28d1d47a
tree6112c94ed0f0597cd1e8aa284abbc397619ae648tree | snapshot
parenta2a0bdf1989c38ca2fc356edd23a114172ee09a2commit | diff
drm/amdgpu: Add MES KIQ clear to tell RLC that KIQ is dequeued

[Why]
As MES KIQ is dequeued, tell RLC that KIQ is inactive

[How]
Clear the RLC_CP_SCHEDULERS Active bit which RLC checks KIQ status
In addition, driver can halt MES under SRIOV when unloading driver

v2:
Use scheduler0 mask to clear KIQ portion of RLC_CP_SCHEDULERS

Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Reviewed-by: Horace Chen <horace.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c diff | blob | history
Domain: System / Kernel;