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(parent: 4c3aeb8) | patch
RISC-V: Add DT documentation for SiFive L2 Cache Controller
authorYash Shah <yash.shah@sifive.com>
Mon, 6 May 2019 10:48:39 +0000 (16:18 +0530)
committerPalmer Dabbelt <palmer@sifive.com>
Fri, 17 May 2019 03:42:13 +0000 (20:42 -0700)
commit5545b6d1ba25ce4a3a339b1edb760e666e693599
treef0578abef4b66e0aaf6ffcf087df6a2a3643183btree | snapshot
parent4c3aeb82a0f4612bf0d94fbf74c3738db2c32fe5commit | diff
RISC-V: Add DT documentation for SiFive L2 Cache Controller

Add device tree bindings for SiFive FU540 L2 cache controller driver

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt [new file with mode: 0644] blob
Domain: System / Kernel;