KARO TX25: Fix NAND Flash R/W cycle times
authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Wed, 8 Aug 2012 03:55:32 +0000 (03:55 +0000)
committerStefano Babic <sbabic@denx.de>
Sun, 23 Sep 2012 17:57:13 +0000 (19:57 +0200)
commit5527024fdb10798d2975197f287457b29e2d4084
tree2255a6b8aab740717826f9b28462fdb8baa82529
parent362635bd50e386770ebaa2d5d090eb8cbf96430b
KARO TX25: Fix NAND Flash R/W cycle times

The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W
cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using
the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle)
resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses.

This patch fixes this issue by setting the NFC clock to the highest frequency
complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: John Rigby <jcrigby@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Daniel Gachet <Daniel.Gachet@hefr.ch>
Acked-by: Stefano Babic <sbabic@denx.de>
board/karo/tx25/lowlevel_init.S