drm/i915: Workaround erratum on i830 for TAIL pointer within last 2 cachelines
authorChris Wilson <chris@chris-wilson.co.uk>
Wed, 22 Dec 2010 14:04:47 +0000 (14:04 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 11 Jan 2011 20:35:41 +0000 (20:35 +0000)
commit55249baaa5cd188ebd9acdb047eeaed8092e4a93
treeec52e1bdb516ce0bd259614b3c068960450b9236
parent35c3047ad15849335242b847c94f180ef45db490
drm/i915: Workaround erratum on i830 for TAIL pointer within last 2 cachelines

On i830 if the tail pointer is set to within 2 cachelines of the end of
the buffer, the chip may hang. So instead if the tail were to land in
that location, we pad the end of the buffer with NOPs, and start again
at the beginning.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/intel_ringbuffer.c
drivers/gpu/drm/i915/intel_ringbuffer.h