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(parent: d80a32f) | patch
clk: tegra: Fix cclk_lp divisor register
authorMichał Mirosław <mirq-linux@rere.qmqm.pl>
Tue, 19 Sep 2017 02:48:10 +0000 (04:48 +0200)
committerThierry Reding <treding@nvidia.com>
Wed, 1 Nov 2017 14:00:06 +0000 (15:00 +0100)
commit54eff2264d3e9fd7e3987de1d7eba1d3581c631e
treeefc64cd2a02c839a6fb1a657da81ab76ec7cfdf2tree | snapshot
parentd80a32fe98b7ce428669b774c3d10ecae3bc6e6dcommit | diff
clk: tegra: Fix cclk_lp divisor register

According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.

Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra30.c diff | blob | history
Domain: System / Kernel;