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(parent: 39173f2) | patch
drm/amd/display: Fix DCN2.1 default DSC clocks
authorMichael Strauss <michael.strauss@amd.com>
Thu, 17 Nov 2022 15:40:46 +0000 (10:40 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 6 Dec 2022 15:16:02 +0000 (10:16 -0500)
commit54e9ea3d5dc8f215abe53c355ddc70c18e0d3329
tree0498e81916ae18bd521e896f95b10b5ab8480dd9tree | snapshot
parent39173f248a5416286c7f42961b717ee39e0e0d1fcommit | diff
drm/amd/display: Fix DCN2.1 default DSC clocks

[WHY]
Low dscclk in high vlevels blocks some DSC modes.

[HOW]
Update dscclk to 1/3 of dispclk.

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c diff | blob | history
Domain: System / Kernel;