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[AggressiveInstCombine] Add `udiv` and `urem` instrs to TruncInstCombine DAG
authorAnton Afanasyev <anton.a.afanasyev@gmail.com>
Tue, 7 Sep 2021 10:16:55 +0000 (13:16 +0300)
committerAnton Afanasyev <anton.a.afanasyev@gmail.com>
Fri, 10 Sep 2021 17:29:08 +0000 (20:29 +0300)
commit54d8ebbbfdb348a6d0354fe7909d9ab146dada5b
tree0a26e713243dda58bde8716f62fa39f5011347aetree | snapshot
parentea7b2c147fefece043f35d150652d50357250e96commit | diff
[AggressiveInstCombine] Add `udiv` and `urem` instrs to TruncInstCombine DAG

Add `udiv` and `urem` instructions to the DAG post-dominated by `trunc`,
allowing TruncInstCombine to reduce bitwidth of expressions containing these
instructions. It is sufficient to require that all truncated bits of both
operands are zeros: https://alive2.llvm.org/ce/z/yiithn
(`urem` case is identical).

Differential Revision: https://reviews.llvm.org/D109515
llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp diff | blob | history
llvm/test/Transforms/AggressiveInstCombine/trunc_udivrem.ll diff | blob | history
Domain: System / Toolchain;