ARM: dts: AM57xx/DRA7: Update SoC voltage rail limits to match data sheet

ARM: dts: AM57xx/DRA7: Update SoC voltage rail limits to match data sheet

As per the data sheet starting from SPRUHQ0H (Nov 2015 - Latest[1]),
VDD_CORE can vary from 0.85v to 1.15v for AVS class0. VDD GPU/DSP
et.al. can range from 0.85v to 1.25V with AVS class0

Since dynamic voltage scaling is disabled for DRA7/AM57xx SoCs for
all SoC rails other than MPU, the bootloader is responsible for
setting up the AVS class0 voltage, however, with wrong voltage machine
constraints in dtb, regulator framework will lower the voltage below
the required voltage levels for certain samples in production flow.
This can cause catastrophic failures which can be pretty hard to
identify.

Update board files which don't match required specification.

[1] http://www.ti.com/product/AM5728/datasheet/specifications#SPRT637-7340

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>