Sync may31 release/8.0-tizen (#510)

Sync may31 release/8.0-tizen (#510)

* [RISC-V] Enable On Stack Replacement (#96558)

* [RISC-V] Implement On Stack Replacement

Note: Pinned local test is failing.

* [RISC-V] Apply suggestions from code review

Co-authored-by: Tomasz Sowiński <tomeksowi@gmail.com>
* [RISC-V] apply jit-format

* [RISC-V] Cosmetic changes after code review

* [RISC-V] Changes assuming memory page is always equal 4KiB

* [RISC-V] Remove stack probing

* [RISC-V] Replace GetEmitter() with emit

* [RISC-V] Sync frame type 1 in genPushCalleeSavedRegisters with genPopCalleeSavedRegisters

* [RISC-V] Fix assembly emmited by genStackProbe

* [RISC-V] Apply jit-formatter

---------

Co-authored-by: Tomasz Sowiński <tomeksowi@gmail.com>
* [RISC-V] Added designated output instruction emitters (#96741)

* Added declarations and r-type definition with assert helper

* Added insEncodeITypeInstr

* Added definition of S type instr

* Added definition of U type instr

* Added definition of B type instr

* Added definition of J type instr

* Restructurized bit operations

* Improved checks in insEncode functions

* Fixed some of the encoding methods

* Bugfix

* Fixed comparation sign

* Revert "Fixed comparation sign"

This reverts commit c238b82cf939c19ed55ce9e027fcaf4def6ba064.

* Fixed comparation sign

* Reverted changes in emitOutputInstrJumpDistanceHelper

* Fixed misspell

* Fixes after review

* Fixes in insEncodeJTypeInstr

* Added emitOutput_RTypeInstr

* Added emitOutput_ITypeInstr

* Added emitOutput_STypeInstr

* Added emitOutput_UTypeInstr

* Added emitOutput_BTypeInstr

* Added emitOutput_JTypeInstr

* Fixes in emitOutput_ methods

* Replaced reloc with new code

* Removed invalid code

* Added emit output rellocation

* Minor changes

* Added emitOutputInstr_Addi8

* Implemented further addi32

* Reverted changes from la

* Fixed format bug

* Fixed comment

* Renamed some of the emitters

* Added some comments

* Improved implementation and finished addi32

* Microimprovements

* Quickfix to upperNBitsOfWord

* Finished substituting instr_optsi

* Fixed bug in mask

* Added emitOutputInstr_OptsRcReloc and prelimiary parent function

* Added emitOutput_OptsRcNoReloc

* Improvements in OptsRc

* Fixes and introduced an emitOutputInstr_OptsRc

* Added emitOutputInstr_OptsRl and removed unused args from other functions

* Added emitOutputInstr_OptsRlReloc

* Finished emitOutputInstr_OptsRcNoReloc

* Fixed bugs and finished opts rl

* Added emitOutputInstr_OptsJalr

* Added emitOutputInstr_OptsJalr8

* Added special comparation inverter

* Add emitOutputInstr_OptsJalr24

* Added emitOutputInstr_OptsJalr28

* Improved emitOutputInstr_OptsJalr28

* Enabled new opts jalr impl

* Added emitOutputInstr_OptsJCond

* Added emitOutputInstr_OptsJ

* Replaced old code with the new one

* Added emitOutputInstr_OptsC

* Fixed last piece of switch

* Removed old code

* Simplified code

* Other fixes

* Fixes in emitOutput_* instr

* Fixed bitmask bug

* Added temporary reinforced assers

* Added shift ins

* Improved shift func

* Inserted shift func

* Fixed minor bug

* Other fixes

* Added checks to r type emitter

* Improved sanity checks in the emitOutput_RTypeInstr

* Added ITypeInstr sanity checks

* Moved ITypeInstr_Shift sanity Check

* Added comment to the emitriscv64

* Added S-type sanity checks

* Removed Shift ITypeInstr Variant

* Fixes

* Added BType sanity check

* Added csr operations to sanity checks

* Added ITypeInstr sanity check

* Fixes

* Removed duplicated code

* Fixed bug in noreloc

* Removed dead asserts

* Removed now unused asserts

* Fixed format

* Fixed missing const

* Removed useless ifdef

* Fixed missing asserts

* Added a new assert

* Added zero assert

* Removed useless FALLTHROUGH statements

* Added trimmers

* Added explicit signed integers trimming

* Fixes to prev commit

* Added castFloatOrIntegralReg and fixed invalid asserts

* Renamed upper word helpers

* Spell fix

* Moved castFloat... to the emitter

* Changes after code review

* Removed bitcast

* Added additional check

* Removed unnecessary reinterpret casts

* Removed redundant asserts

---------

Co-authored-by: Grzegorz Czarnecki <g.czarnecki@samsung.com>
* [RISC-V] Fix errors in crosgen2 for risc-v (#97368)[PARTIALLY]

Partially cherry-picked commit: jit, pal, vm parts. Tools part need to be cherry-picked further.

* [RISC-V] Fix crossgen2

* [RISC-V] Fix typo in codegen

* [RISC-V] Update assert to support all rel insts

* [RISC-V] Fix helper function call

* [RISC-V] Update GetRISCV64PassStructInRegisterFlags

* [RISC-V] Fix int arg reg passing for float type

A failure during crossgen2 SPC.dll
`System.Diagnostics.Tracing.NativeRuntimeEventSource:LogThreadPoolWorkerThreadAdjustmentStats(double,double,double,double,double,double,double,double,double,ushort,ushort)`

* [RISC-V] Update EPILOG_WITH_TRANSITION_BLOCK_RETURN

* [RISC-V] Update indentation in dump

* [RISC-V] Fix stubs

* [RISC-V] Fix virtualcallstubcpu

* [RISC-V] Update a comment

* [RISC-V] Update RO data block

* [RISC-V] Fix data overwrites

* [RISC-V] Fix typo

* [RISC-V] Fix register number of A3

* [RISC-V] Code Formatting

* [RISC-V] Fix format and typos

* Revert "[RISC-V] Fix int arg reg passing for float type"

This reverts commit 381858cb2335782d66e8a6439db9c6f053adff21.

* [RISC-V] Fix a typo in a comment

* [RISC-V] Fix error when arg type and arg reg mismatch

* [RISC-V] Rename according to review

* [LoongArch64] Remove LA64 specific handling for unspilling

* [RISC-V] Fix gc-related bugs in risc-v emitter (#98226)

* [RISC-V] Fix mistakes in emitter

* Revert "[RISC-V] Added designated output instruction emitters (#96741)"

This reverts commit 77fd98c8fb245b30b24b8eeaf577b0a457a4449c.

* Revert "Revert "[RISC-V] Added designated output instruction emitters (#96741)""

This reverts commit ecc044d4e6082c0f727bd7e36d53878416cf4207.

* [RISC-V] Sync emitOutputIns with the latest ref branch

* [RISC-V] Formatted code

* [RISC-V] Fixes

* [RISC-V] Fixed sign cast in assert code len

* [RISC-V] Readed assert

* [RISC-V] Fixed fence sanity check and removed fence_i

---------

Co-authored-by: Dong-Heon Jung <clamp03@gmail.com>
* [RISC-V] Set setFrameRequired like the other archs (#98535)

* [RISC-V] Remove unnecessary assertion from emitOutputInstr (#98484)

* Remove unnecessary assertion

It fired a false positive when W^X was enabled

* Use uint32 write instead of memcpy to be faster

There shouldn't be a problem when we introduce compressed instructions, VF2 supports unaligned stores (sw)
Also, replace compile-time conditions with static_asserts.

* Bring back memcpy because plain RV64 ISA allows trapping on misaligned load/stores

* [RISC-V] Check DivideByZeroException before generating check for unsigned div/mod (#98648)

* Generate check for unsigned divide by zero only when ExceptionSetFlags::DivideByZeroException is present

Not doing so caused JITting on FullOpts fail on assert(add->acdUsed) in genJumpToThrowHlpBlk_la when the DivByZero check was optimized out as a result of #98113

* Change check for GT_DIV or GT_MOD in LSRA to look the same as CodeGen::genCodeForDivMod

* Don't set RM field when fcvt doesn't round (#98857)

CPUs and QEMU tend to ignore it but according to RISC-V ISA fcvt.d.s or fcvt.d.w[u] never round so it is an error. Besides, external disassemblers choke on it.

* Remove redundant check for DivideByZeroException for unsigned division/modulo. (#99228)

The check was already generated at the beginning of the branch for integer operations.

* [RISC-V] Use getUnrollThreshold() to get unroll limits (#98798)

* [RISC-V] Use getUnrollThreshold() to get unroll limits

* Modify formatting

---------

Co-authored-by: monstercat <45393763+monstercatss@users.noreply.github.com>
* [RISC-V] Fix calculating remainingSPSize (#99288)

* [RISC-V] Fix initReg usage in genPushCalleeSavedRegisters (#99353)

* [RISC-V] Fix bug in crossgen2 (#99394)

* [RISC-V] Fix alignment for vector types (#99589) [PARTIALLY]

Partially cherry-pick: vm & libraries take, tools need to be picked further due to dependency on #95188, which cause build error.

For vector256 and vector512, set possible max alignment value.

Reference
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc

Revert tools part of "[RISC-V] Fix alignment for vector types (#99589)"

* [RISC-V] Avoid using native layout info to calculate register flags for small structs where possible (#97877)

* Remove initializing native layout info for small structs during type load

Managed->managed calling convention should not depend on native info which is used for interop marshalling with unmanaged code which is above the type loader.

* Don't use native layout in GetRiscV64PassStructInRegisterFlags unless we're calculating flags for a native value type

* Remove redundant assertions, AsNativeValueType() has the same

* Cover implied repeated fields, a.k.a fixed arrays, in when calculating small struct flags from non-native layout

* Cover implied repeated fields, a.k.a fixed arrays, also in non-native branch of IsRiscV64OnlyOneField

* [LoongArch64] Avoid using native layout info to calculate register flags for small structs where possible. (#99854)

* Also merge 'MethodTable::IsLoongArch64OnlyOneField()' and 'MethodTable::IsRiscV64OnlyOneField()' into 'MethodTable::IsOnlyOneField()'.

Co-authored-by: Jan Kotas <jkotas@microsoft.com>
* [RISC-V] Add missed instructions (#99948)

In genInstrWithConstant, loadType and zero-extends are missed.
- lbu, lhu and lwu

* LogicalName added for EmbeddedResource (#99999)

* LogicalName added for EmbeddedResource

* Disable test22888 on Mono

Mono does not support collectible assemblies that this test is exercising.

---------

Co-authored-by: Jan Kotas <jkotas@microsoft.com>
* Add arch_info for TARGET_RISCV64 (#100341)

* [RISC-V] Fix intermittent failures due to unalignment access (#100431)

* [RISC-V] Fix intermittent failures due to unalignment access

* [RISC-V] Update for ALIGN_ACCESS

* Apply suggestions from code review

---------

Co-authored-by: Jan Kotas <jkotas@microsoft.com>
* Enable tail call generation for test Runtime_87393 (#100593)

To pass the test needs to be built with --tailcalls compiler flag enabled.

* [RISC-V] Fix assertion for auipc and lui (#100578)

* [RISC-V] Fix assertion for auipc and lui

* [RISC-V] Update codegenriscv64

* [RISC-V] Remove an assert

* [RISC-V] Fixed printing jump destinations in disassembler on release (#100967)

* [RISC-V] Fixed printing jump destinations in release mode in disasm

* [RISC-V] Fixed cast type

* [RISC-V] Simplify flags for passing struct in registers (#100080)[PARTIALLY]

* [RISC-V] Fix struct info value in crossgen2

* [RISC-V] Fix assertion in crossgen

Asserts in `./Interop/StructMarshalling/PInvoke/MarshalStructAsLayoutExp/MarshalStructAsLayoutExp.sh`
Error message is
`Assertion failed 'roundUp(structSize, TARGET_POINTER_SIZE) == roundUp(loadExtent, TARGET_POINTER_SIZE)' in 'Managed:MarshalStructAsParam_AsExpByVal(int)' during 'Morph - Global' (IL size 2208; hash 0x9fd9734a; MinOpts)`
Copied missed codes of GetRiscV64PassStructInRegiste in vm to crossgen2

* Check size in GetRiscV64PassStructInRegisterFlags early, use named constant

* Simplify managed branch of GetRiscV64PassStructInRegisterFlags

* Fix assert IsPrimitiveType for 2nd field

* Handle empty structs

* Apply FIELD_SIZE_IS8 flags only when there's at least one float

* Handle empty array struct elements

* Enregister any field type <= 8 bytes, not just primitives; i.e. pointers and refs are also OK

* Simplify native layout branch of GetRiscV64PassStructInRegisterFlags

* Rewrite native branch to look at only at native layout info

* Calculate flags already in GetFlattenedFieldTypes to avoid returning fake CorElementTypes from native branch

* Ignore empty structs during field flattenting because RISC-V calling convention tells us to

* Simplify crossgen2 GetRISCV64PassStructInRegisterFlags, make C++ and C# versions of this method look more alike

* Remove early exit if nFields == 0 because it wasn't doing much, the loop won't do any work if there's no fields

* Return early from HasImpliedRepeatedFields. GetApproxFieldDescListRaw() is null on empty structs, which crashes pFieldStart->GetFieldType()

* Cleanup GetRiscV64PassStructInRegisterFlags call sites

* Stackalloc field types to avoid GC allocations

---------

Co-authored-by: Dong-Heon Jung <clamp03@gmail.com>
* [RISC-V] Fix FEATURE_MULTIREG_RETURN definition (#101642)

* [RISC-V] fix rm field in riscvd instruction (#101908)

Changed rm from 1 to 0.
Fixed instructions:
- fcvt.d.w
- fcvt.w.d
- fcvt.d.wu
- fcvt.wu.d
- fcvt.d.s
- fcvt.s.d

* [LoongArch64] Simplify flags for passing struct in registers. (#102041)[PARTIALLY]

Partialli cherry-picked commit: took vm part, reject tools part which has only loongarch64 fixes.

Change-Id: Idbe644c0bc5baeb53a53e16731824e28aacf67a0

* [RISC-V] Support SV48 Virtual Memory Layout (#101966)

* Fix VirtualCallStubManager stats capturing on EE shutdown (#102073)

* Fix VirtualCallStubManager stats capturing on EE shutdown

Before this change logging stats to StubLog file doesn't work because on EE shutdown
we don't shut down manager. Since it's only about logging we can perform uninit earlier.

* Address code review comments

* Fix few gcc build warnings for RISC-V (#102426)

* [RISC-V] Fix invalid operand register in the emitted addition/subtraction code (#102074)

* [RISC-V] Added sext_w pseudoinstruction

* [RISC-V] Inserted INS_sext_w pseudoinstruction

* [RISC-V] Started implementing new overflow logic

* [RISC-V] Finished preliminar implementation of bound checks

* [RISC-V] Fixed invalid 32-bit instruction

* [RISC-V] Fixed 32-bit addition overflow check assert

* [RISC-V] More fixes in emitter

* [RISC-V] Additional fixes

* [RISC-V] Fixed triple same register problem in emitInsTernary addition and subtraction logic

* [RISC-V] Added sext.w to disassembler

* [RISC-V] Added comments

* [RISC-V] Formatted code

* [RISC-V] Fixed bug

* [RISC-V] Fixed other bug

* [RISC-V] Fixed bug causing the int32's version to never be emitted

* [RISC-V] Fixed assert

* [RISC-V] Improved comment

* [RISC-V] Fixed comment

* [RISC-V] Fixed temp reg acquiring

* [RISC-V] Removed asserts

* Fixed NodeInternalRegister's GetSingle method's comment

* [RISC-V] Revoked more changes

* [RISC-V] Revoked more changes

* [RISC-V] Embedded sext_w into codegen

* [RISC-V] Fixed some comments

* [RISC-V] Added additional comment

* [RISC-V] Improvements

* [RISC-V] Added old comment

* [RISC-V] Improve code generating resolve stub assembly (#102318)

* [RISC-V] Improve code generating resolve stub assembly

This change replaces magic numbers with proper offsetofs and use compile time asserts instead runtime ones.
That should make developers life easier in case of debugging or changing resolve stubs assembly.

* Move annotation and don't check same thing many times

* [RISC-V] Add pseudoinstructions to disassembler (#102260)

* [RISC-V] Reworked emitDispInsName a bit to ease further development

* [RISC-V] Little improvements

* [RISC-V] Refactored code

* [RISC-V] Added mv and nop pseudoinstructions to disasm

* [RISC-V] Added branch pseudos to disasm

* [RISC-V] Removed dead code

* [RISC-V] Fixes

* [RISC-V] Added j pseudoinstruction to disasm

* [RISC-V] Improved readability

* [RISC-V] Fixed mov pseudoinstruction

* Revert "[RISC-V] Fixed mov pseudoinstruction"

This reverts commit a011c43cb75ef7fff976e6804f6474417a18eda8.

* [RISC-V] Fixed mov printing name

* [RISC-V] After review changes

* [RISC-V] More fixes after review

* [RISC-V] Adjusted 32-bit shift disasm to changes

* [RISC-V] Fixed bug

* [RISC-V] Fixed comment

* [RISC-V] Changed constants' literal type

* [RISC-V] Added more constants

* [RISC-V] Reinforced printing 1

* [RISC-V] Reinforced printing 2

* [RISC-V] Fixed bug

* [RISC-V] Resolved more bugs

* [RISC-V] Removed dead assert

* [RISC-V] Fix Interop/StructPacking/StructPacking.dll Failure (#102864)

---------

Co-authored-by: Tymoteusz Wenerski <t.wenerski@partner.samsung.com>
Co-authored-by: Tomasz Sowiński <tomeksowi@gmail.com>
Co-authored-by: Grzegorz Tomasz Czarnecki <grzegorz.czarnecki.2021@gmail.com>
Co-authored-by: Grzegorz Czarnecki <g.czarnecki@samsung.com>
Co-authored-by: Dong-Heon Jung <clamp03@gmail.com>
Co-authored-by: JongHeonChoi <j-h.choi@samsung.com>
Co-authored-by: Min <45393763+MinxuanZ@users.noreply.github.com>
Co-authored-by: monstercat <45393763+monstercatss@users.noreply.github.com>
Co-authored-by: Xu Liangyu <xuliangyu@loongson.cn>
Co-authored-by: Jan Kotas <jkotas@microsoft.com>
Co-authored-by: rzsc <160726116+rzsc@users.noreply.github.com>
Co-authored-by: t-mustafin <66252296+t-mustafin@users.noreply.github.com>
Co-authored-by: SzpejnaDawid <166010737+SzpejnaDawid@users.noreply.github.com>
Co-authored-by: yurai007 <dawid_jurek@vp.pl>
Co-authored-by: Gleb Balykov <g.balykov@samsung.com>