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[DAGCombiner] allow store merging non-i8 truncated ops
authorSanjay Patel <spatel@rotateright.com>
Wed, 26 Aug 2020 19:21:54 +0000 (15:21 -0400)
committerSanjay Patel <spatel@rotateright.com>
Wed, 26 Aug 2020 19:23:08 +0000 (15:23 -0400)
commit54a5dd485c4d04d142a58c9349ada0c897cbeae6
tree632df33a6b50036f02976bc51bf75d808cdea632tree | snapshot
parentc6c292da910578bdec76616c606da2d79b730667commit | diff
[DAGCombiner] allow store merging non-i8 truncated ops

We have a gap in our store merging capabilities for shift+truncate
patterns as discussed in:
https://llvm.org/PR46662

I generalized the code/comments for this function in earlier commits,
so we only need ease the type restriction and adjust the address/endian
checking to make this work.

AArch64 lets us switch endian to make sure that patterns are matched
either way.

Differential Revision: https://reviews.llvm.org/D86420
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff | blob | history
llvm/test/CodeGen/AArch64/merge-trunc-store.ll diff | blob | history
llvm/test/CodeGen/X86/stores-merging.ll diff | blob | history
Domain: System / Toolchain;