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(parent: 8310e32) | patch
RDMA/mlx5: Expose TIR and QP ICM address for sw_owner_v2 devices
authorAlex Vesker <valex@nvidia.com>
Thu, 3 Sep 2020 07:38:57 +0000 (10:38 +0300)
committerJason Gunthorpe <jgg@nvidia.com>
Fri, 18 Sep 2020 12:40:41 +0000 (09:40 -0300)
commit54a38b6627d3f11028f806f1f529a68453a77f46
treea12de1ea86394d49e50071a08f8ba4137563fa63tree | snapshot
parent8310e327046df6b8d729ffa41ed7cfd6676abc42commit | diff
RDMA/mlx5: Expose TIR and QP ICM address for sw_owner_v2 devices

Expose the ICM address to access TIR and QP, this will allow sw_owned_v2
devices to steer traffic to TIRs and QPs same as done with sw_owner
capability.

Link: https://lore.kernel.org/r/20200903073857.1129166-4-leon@kernel.org
Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
drivers/infiniband/hw/mlx5/qp.c diff | blob | history
Domain: System / Kernel;