MIR: Reject non-power-of-4 alignments in MMO parsing
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 30 Jan 2019 23:09:28 +0000 (23:09 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 30 Jan 2019 23:09:28 +0000 (23:09 +0000)
commit547a83b4ebd1cbbe90b092634bf1d909ded48555
treecd7c41cef8fc587a95986659b0f2cd684767eb4e
parent10f59405ae50568308b713d9dd20eb30625470bd
MIR: Reject non-power-of-4 alignments in MMO parsing

llvm-svn: 352686
22 files changed:
llvm/lib/CodeGen/MIRParser/MIParser.cpp
llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir
llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir [new file with mode: 0644]
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir
llvm/test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir
llvm/test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir
llvm/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir
llvm/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir
llvm/test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir
llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir
llvm/test/CodeGen/X86/GlobalISel/x86-select-srem.mir
llvm/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir
llvm/test/CodeGen/X86/GlobalISel/x86-select-urem.mir