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(parent: 237f4d9) | patch
intel/gen9: Enable MSC RAW Hazard Avoidance
authorAnuj Phogat <anuj.phogat@gmail.com>
Wed, 9 Sep 2020 18:05:18 +0000 (11:05 -0700)
committerAnuj Phogat <anuj.phogat@gmail.com>
Thu, 1 Oct 2020 16:57:50 +0000 (16:57 +0000)
commit545d852a7a7bc8a509d22096bdb7fb578d4bab65
tree05f3f47654ef82e465144df141c11656b879be9dtree | snapshot
parent237f4d9d187ec21d880c7fb4441456d22b4269b6commit | diff
intel/gen9: Enable MSC RAW Hazard Avoidance

Workaround # 22011374674
Applied to i965, iris and anv drivers
No performance impact is observed with WA.

Cc: mesa-stable
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/gallium/drivers/iris/iris_state.c diff | blob | history
src/intel/vulkan/genX_state.c diff | blob | history
src/mesa/drivers/dri/i965/brw_defines.h diff | blob | history
src/mesa/drivers/dri/i965/brw_state_upload.c diff | blob | history
Domain: Graphics System / GL;