drm/msm/dpu: update UBWC config for sm8150 and sm8250
authorJonathan Marek <jonathan@marek.ca>
Sat, 11 Jul 2020 00:47:25 +0000 (20:47 -0400)
committerRob Clark <robdclark@chromium.org>
Fri, 31 Jul 2020 13:46:16 +0000 (06:46 -0700)
commit544d8b96150dea3d439dcaf66ac01eca58f4016c
treeafd07972a0384d6214528a5062fd1b42cb75a6b4
parentde321dcc23d51b791ccba6479fcebc797927efbf
drm/msm/dpu: update UBWC config for sm8150 and sm8250

Update the UBWC registers to the right values for sm8150 and sm8250.

This removes broken dpu_hw_reset_ubwc, which doesn't work because the
"force blk offset to zero to access beginning of register region" hack is
copied from downstream, where mapped region starts 0x1000 below what is
used in the upstream driver.

Also simplifies the overly complicated change that was introduced in
e4f9bbe9f8beab9a1ce4 to work around dpu_hw_reset_ubwc being broken.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c