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(parent: 9f4b61b) | patch
powerpc/64s: micro-optimise __hard_irq_enable() for mtmsrd L=1 support
authorNicholas Piggin <npiggin@gmail.com>
Fri, 4 May 2018 17:19:28 +0000 (03:19 +1000)
committerMichael Ellerman <mpe@ellerman.id.au>
Sun, 3 Jun 2018 10:40:26 +0000 (20:40 +1000)
commit54071e4176f0cedc39809f51cdbc78edd38ee77a
treebee09315c63fd8bcdc5c14ec844b8fdbab06099dtree | snapshot
parent9f4b61b2777dfd1692189ab3e38f8eb7dc669512commit | diff
powerpc/64s: micro-optimise __hard_irq_enable() for mtmsrd L=1 support

Book3S minimum supported ISA version now requires mtmsrd L=1. This
instruction does not require bits other than RI and EE to be supplied,
so __hard_irq_enable() and __hard_irq_disable() does not have to read
the kernel_msr from paca.

Interrupt entry code already relies on L=1 support.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
arch/powerpc/include/asm/hw_irq.h diff | blob | history
Domain: System / Kernel;